This invention relates to a lateral bipolar transistor and its manufacturing method. More particularly, the invention relates to a lateral bipolar transistor made in a semiconductor layer on an insulating film and can decrease the parasitic base resistance, and a method for manufacturing same.
For improving RF basic characteristics of a bipolar transistor, such as cut-off frequency (also called gain-bandwidth product) (f.sub.T) and maximum oscillation frequency (f.sub.max), it is effective to decrease parasitic capacitance between electrodes. When a lateral bipolar transistor is made on a SOI (silicon on insulator) substrate, the capacitance between electrodes is reduced remarkably as compared with a bipolar transistor made on a bulk substrate, and a high-performance bipolar transistor is realized.
Japanese Patent Laid-Open Publication No. H4-29126 may be the first literature disclosing a structure and a manufacturing method of a conventional lateral bipolar transistor. FIG. 36 is a plan view schematically showing construction of a central part of the bipolar transistor. Here is shown the part of a semiconductor layer of the lateral bipolar transistor made on an insulating layer. The lateral bipolar transistor 200 has a cross-shaped semiconductor layer, and a pn junction between an n.sup.+ -type emitter region and a p-type base region is made in a region 204 near the center of the cross. The n.sup.+ -type emitter region extends to the left on the drawing sheet, and joins an n.sup.+ -type external emitter region 202. The p-type base region extends both upward and downward on the drawing sheet, and joins a p-type link base region 206 and a p.sup.+ -type external base region 208 at each end. On the opposite side of the emitter region, an n.sup.- -type collector region 210 is provided. It extends to the right on the drawing sheet, and joins an n.sup.+ -type external collector region 212.
Used for manufacturing the transistor 200 is a method which first makes the cross-shaped semiconductor region, then makes a mask in another step, and makes the base in self alignment with side walls thereof.
However, in the transistor 200 manufactured by this method, the length of the junction between the link base region and the external emitter region 202 (the portion shown by bold lines X in FIG. 36) inevitably becomes large. Consequently, there was the problem that the parasitic pn junction capacitance increased and caused the gain to be decreased during operation under high frequencies.
Another problem was that the current gain h.sub.FE could not be enlarged because a lot of electrons were injected toward the link region 206. The cause was also existence of the parasitic p-n junction.
Another problem was that the length of the pn junction made in the device varied by misalignment of the resist pattern determining the region for ion implantation of the emitter impurity and caused fluctuation in the above-mentioned characteristics.
On the other band, although the width W of the link base region 206 is made relatively large, impurities cannot be implanted in self-alignment into the region, and misalignent of the resist pattern determining the region of ion implantation (of the impurity) invites fluctuation in the external base resistance (value). Fluctuation of the characteristics inevitably results in degrading the performance of the matching require circuit, the one made up of a plurality of devices chosen by the calculation that a certain output signal will be obtained in response to a certain input signal.
As discussed above, the lateral bipolar transistor having the construction shown in FIG. 36 involved the problems: large parasitic capacitance between the emitter and the base; low current gain; and difficulty in reproducible reduction of the base resistance.
Japanese Patent Laid-Open Publication No. H2-46735 is another literature disclosing a conventional lateral bipolar transistor. FIG. 37 is a plan view schematically showing a central part of the transistor disclosed in the literature.
Here again, the lateral bipolar transistor 300 has a cross-shaped semiconductor layer including a p-n junction of an n.sup.+ -type emitter region and a p-type base region in a central zone 304 of the semiconductor layer. Also formed are an n.sup.+ -type external emitter region 302, p-type link base region 306, p.sup.+ -type external base regions 308, n.sup.- -type collector region 310 and n.sup.+ -type external collector region 312.
For manufacturing the transistor 300, after making a mask on the semiconductor layer and a base in self alignment with side walls of the semiconductor layer, a pattern of the external region is transferred onto the semiconductor layer.
In the transistor made the method, almost no parasitic junction is formed between the link base region 306 and the external emitter region 302, and most part of injected electrons flow toward the collector.
However, the transistor 300 shown in FIG. 37 involved the problem that reduction of the base resistance was difficult. This issue is discussed below.
The link base region 306 of the transistor 300 is made in the following process.
First made is a resist pattern having predetermined openings to determine the external emitter region 302 and the external base regions 308, and it is transfered onto the semiconductor layer. Next made are a resist pattern for implanting a p.sup.+ -type impurity only into the external base regions 308 and a resist pattern for implanting an n.sup.+ -type impurity only into the external emitter region 302. This process needs aliment of these resist patterns. Taking account of the alignment accuracy and fluctuation in size, the distance L between the external emitter region 302 and each external base region 308 can be decreased to 0.3 .mu.m, approximately. To do so, however, the process needs a lithography apparatus and lithographic processing with an ultra-high controlability, and it is not a practical size for this process.
Another problem is high base resistance. Impurity concentration of the link base region is about 10.sup.18 cm.sup.-3 approximately equal to that of the internal base region. The width W of the link base region 306 is approximately equal to that of the base width, nanely, 0.1 .mu.m. Then length L of the link base region 306 is determined by the resolution limit and the alignment accuracy of the lithography which determine the distance between the external emitter region 302 and the external base region 308. That is, these factors compel the transistor 300 to accept a low impurity concentration of the link base region 306, a smaller width W thereof, and a longer length L there of to a certain extent. Therefore, the transistor 300 involved the problem that the resistance of the link base region was very high, and its inherent high-performance characteristics could not be brought out
A manufacturing method for reducing the resistance of the link base region is disclosed in U.S. Pat. No. 5,629,554. As a third conventional technique, this is explained below.
The manufacturing method is configured to first form a mask on the semiconductor layer, next form external base regions by conducting photolithography, ansotropic etching and p.sup.+ -type doping, and finally form an external emitter region by conducting n-type polysilicon deposition, photolithography, and anisotropic etching.
That is, according to the method, a mask is made on the semiconductor layer by first lithography, then the external base regions are made in the semiconductor layer by second lithography, and the external emitter region is made in another layer (for example, n-type polysilicon layer) other than the semiconductor layer by third lithography. By determining the distance between the external emitter region and the external emitter region by the second lithography, it becomes possible to make the gap between the external emitter region and the external base region smaller than the minimum dimensional limit by techniques relying lithography.
However, this manufacturing method also involved the problem that it needed an apparatus and a process enabling lithography with a very high accuracy, taking account of alignment accuracy and fluctuation in size, similarly to the transistor shown in FIG. 37.
Moreover, these conventional manufacturing methods involved the problem that characteristics were variable due to asymmetry of positions for making the external emitter region, external base region and external collector region. This is derived from the need for at least three kinds of resist patterns for making these three regions. For example, this results in varying the link base resistance due to misalignment between the resist pattern for the external emitter region and the resist pattern for the external base regions. Similarly, any offset of the center axis of the external collector region from the center axis of the external emitter region invites variation of the characteristics.